Comparative Study of Different Modes for Reducing Leakage and Dynamic Power through Layout Implementation

Smt. Sarita Chauhan, Anand Kumar Gupta, Falak Jahan, Rajesh Biyaniya, Surbhi Pathak

Leakage power has become a serious concern in nanometer CMOS technologies and is a very important issue in hardware and software design. The leakage power increases as technology is scaled down. However, with the continuous trend of technology scaling, it is becoming a main contributor to power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. In advanced integrated circuits, more power is consumed. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth, stacking transistors etc. In this paper, new methods have been proposed for that. The proposed methods will be compared with the previous existing leakage reduction techniques. This paper includes a new technique called dual stack for reducing leakage and dynamic power and comparison of this technique with old techniques.