Design and Optimization of a Low DC Offset in Implanted System for ENG Recording Based on Velocity Selectivity Method

Assad I. K. Al-Shueli

The major target of this paper is the design of advance signal processing system based on minimized length of bits required for digital-to-analogy converter (DAC) for velocity selectivity recording (VSR) approach. The main application of this device is peripheral nerves recording (electroneurogram-ENG) by exploring a spectral analysis for the propagation of neural activities in the velocity domain recording using VSR in implantable application. This research adapted a flexible, compact, and energy efficient dc offset removal circuit. An optimization design has been used based on best possible process involving linearity and area is thus suggested. The system process acquired using this approach were characterized as having a 10-bit signal processing for DAC resolution, with 1.4 mA rms output current, with minimum size around 0.02 mm² of chip area, using FPGA board as prototype design. This paper also explores the design temperature vibration in online recording; minimization the output DC offset decrease the heat emission which is significantly for long term implementation applications. This study proposed an analysis circuit configuration demonstrate that this approach could achieve a small DC offset error, with small size required.