Design of schematic synchronously clocked JK flip-flop using CMOS technology

Duy Khanh Pham

Flip-flop, CMOS technology, VLSI design, low power, Cadence.

Nowadays, CMOS technology has played a vital role in implementing high density, high-speed, and low-power VLSI systems. Designing IC chip basically consists of a numerous numbers of logic gates which are integrated inside. Reducing the power dissipation of the circuit is always a big challenge to any circuit designer. There are many different techniques to reduce power consumption based on circuit level, architecture, layout design, and process technology. Universal JK flip-flop (JK-FF), also known as a latch circuit, is an improved version of the SR flip-flop and can be operated with both high active inputs. JK-FFs is widely used in electronic circuits with the main aim to store the state information of the device. The major applications of JK-FF are used for shift registers, data storage (RAM), data transfer, counters, frequency dividers, storage registers, event detectors, data synchronizers, PWM and computer applications. The current paper aims to design schematic synchronously clocked JK-FF using CMOS technology with the number of transistors used less than some other design methods. The schematic, simulation and layout of the proposed design are performed on Cadence software.