Efficient reduction of leakage power in low power VLSI circuits using Sleepy Keeper Approach

Monisha.S, Priya.M, A. Upendra Raju, Uma.V

Voltage Scaling in CMOS circuits will reduce the threshold voltage, however there is an increase in the sub threshold leakage current and hence static power dissipation. This increase in leakage power dissipation is a concern in VLSI design even for the most recent CMOS feature sizes. To reduce this power dissipation an approach called sleepy keeper is used for CMOS circuits. This approach uses two additional transistors along with the traditional sleep transistors. These additional transistors help to save a logic state during the sleep mode.