Low Power and High Speed SAR ADC-A Review

Nishitha Palan, Nidhi Sampath, Pooja Vilekha Burujula

Calibration, comparator, high speed, low power

In the present technical era, with all the technological advancements in wireless communication and Complementary Metal Oxide Semiconductor (CMOS) scaling. It challenges analog designers to improve the Analog to Digital Converter (ADC) architectures. Thus leads their design to demand for a reduction in the power consumption. Along with it, it also calls for higher resolution, speed and smaller area. Analog to digital convertors are mainly power hungry compared to any other blocks in any architecture. Among the different Analog to digital convertors, Successive Approximation Register (SAR) Analog to digital convertor (ADC) is proven to provide results with lower power consumption and lesser area with higher speed and medium accuracy compared to others. So, in this paper, we discuss about the various approaches used in designing Successive Approximation Register Analog to digital convertor to provide an optimized design with low power and high speed.

https://dx.doi.org/10.31873/IJEAS.8.7.03