Redundant Binary Partial Product for Fused add Multiplier to Optimize the Power

Dr.C.Venkatesh, S.Poonkuzhali, M.Moortheeswari

Many Digital Signal Processing (DSP) applications carry out a large number of complex arithmetic operations. Multiplier takes a important role in the performance of the system, thus by optimizing the multiplier the power and area can be reduced. This paper focus on optimizing the power using redundant binary partial product. This implements a new technique called RB encoding, in which the sum of two numbers and there product is multiplied with the multiplier in Modified Booth (MB) form. The RB encoding is used in multipliers with operand, without increasing the delay of partial product accumulation. It is used for both signed and unsigned Radix-4, which is a parallel multiplier. its An efficient multiplier which reduces partial product by N/2, where N is the number of multiplicand. The proposed FAM unit with RB encoding is coded in Verilog, simulated and synthesized using Xilinx ISE tool. The performance of FAM unit with RB encoding is compared with other existing technique in terms of power consumption and critical path. The proposed FAM unit with RB encoding yields considerable reduction in terms of critical delay and power consumption.