Smart Reliable Network on Chip and its Area reduction using Elastic buffer

Meera P Alias, Melvin C Jose

Network on Chip (NoC) is one of the efficient on-chip communication architecture for System on Chip (SoC) where a large number of computational and storage blocks are integrated on a single chip.NoC has more flexibility and reusability when compared with dedicated wires where number of wires increases dramatically as the number of cores grows.In this project 2X2  and 4X4 mesh topology NoC has to be designed and implemented. The proposed NoC is based on adaptive XY routing algorithm. In Adaptive XY algorithm ,if any neighbouring router becomes faulty,faulty link of the router will be bypassed.The area requirements of the NoC is very high.In order to reduce the area,the input and output buffers of the NoC will be replaced with elastic buffers.Inorder to further improve the performance of the NoC ,an arbiter can be introduced.Arbiter is used when many input ports request the same output port and in such cases a priority will be assigned for input ports when they request the same output port.  The NoC’s performance have to  be evaluated and implemented on Spartan3E  field programmable gate array kit.